Differential Static Ultra Low-Voltage CMOS Flip-Flop for High Speed Applications
نویسنده
چکیده
Abstract: In this paper we present a simple ultra low-voltage and high speed D flip-flop. The delay of the static differential flip-flop presented is less than 12% compared to conventional differential CMOS flip-flops. The presented circuits have been simulated using Hspice and are valid for 90nm TSMC CMOS process. The proposed high-speed and ultra low-voltage flip-flop can be used for any digital low-voltage CMOS application.
منابع مشابه
Ultra Low-voltage Differential Static D Flip-Flop for High Speed Digital Applications
In this paper we present an ultra low-voltage and high speed D flip-flop. The flip-flop has an increased current level compared to standard CMOS circuits operating at low supply voltages. The increased current level is obtained by using a synchronized capacitive coupling to a semi floating-gate. The delay of the static differential flip-flop presented is less than 12% compared to conventional d...
متن کاملDesign of a fully-static differential low-power CMOS flip-flop
A fully-static flip-flop structure is proposed and compared to both the conventional CMOS flip-flop and the Cascode Voltage Switch Logic (CVSL) static flip-flop proposed by Yuan and Svensson [I], in terms of speed, power consumption and silicon area. Then an add-and-delay circuit is implemented using all three flip-flop structures to demonstrate the performance of the proposed flip-flop. The ad...
متن کاملStatic Differential Ultra Low-Voltage Domino CMOS logic for High Speed Applications
In this paper we present a novel static differential ultra low-voltage (ULV) CMOS logic style for High-Speed applications . The proposed logic style is aimed for high speed serial adders in ultra low-voltage applications. The differential ultra low-voltage inverter presented have less than 10% of the delay than standard CMOS inverters for supply voltages less than 500mV . The simulated data pre...
متن کاملA dual-pulse-clock double edge triggered flip-flop for low voltage and high speed application
In this paper, a low voltage dual-pulse-clock double edge triggered D'flip-flop (DPDET) is proposed. The DPDET flip-flop uses a split output latch clocked by a short pulse train. Compared to the previously reported double edge triggered flip-flops, the DPDET flip-flop uses only six transistors with two transistors being clocked, operating correctly under low supply voltage. The total transistor...
متن کاملLow Voltage Operation of Master-Slave Flip-Flops for Ultra-Low Power Subthreshold LSIs
In this paper, we investigate low voltage operation of master-slave flip-flops (MSFFs) for ultra-low power subthreshold CMOS LSI families. Static MSFF, which consists of NAND gates, shows the most stable operation, while dynamic MSFFs are unsuitable for low voltage operation because switching gates fail to operate at low voltage. Low voltage limitation of static MSFF depends on that of CMOS gat...
متن کاملذخیره در منابع من
با ذخیره ی این منبع در منابع من، دسترسی به آن را برای استفاده های بعدی آسان تر کنید
عنوان ژورنال:
دوره شماره
صفحات -
تاریخ انتشار 2011